The present invention relates to an image processing apparatus, an image processing method, and a vehicle control apparatus.
Demands for high-speed operations of data processing apparatuses which perform image processing and audio processing have increased year by year. In particular, for an image processing apparatus and an image recognition apparatus that are applied for vehicles, not only high speed processing but also a technique to accurately detect and recognize an object is required.
This trend increases more and more following enlargement of image data due to development of multimedia and enrichment of contents in recent years.
In particular, a huge amount of image data and a huge number of processing times are required to calculate motion information and distance information from high density pixel information in a front monitoring system. Therefore, it is anticipated that high performance will be further required hereafter.
To meet the requirement, Japanese Unexamined Patent Application Publication No. 2003-296096 discloses an arithmetic apparatus in which parallel processing is performed by pipeline processing. A plurality of arithmetic units are coupled in series in Japanese Unexamined Patent Application Publication No. 2003-296096. Arithmetic operation data of a pre-stage arithmetic unit is outputted to a post-stage arithmetic unit.
Japanese Unexamined Patent Application Publication No. 2002-182905 discloses an apparatus in which an arithmetic instruction is performed by a plurality of arithmetic elements. A register can be directly accessed from each of the arithmetic elements in Japanese Unexamined Patent Application Publication No. 2002-182905. The register holds an arithmetic operation result of each arithmetic element.